The present invention relates to a method and a device for supporting high rate data streams, with handling overhead layers thereof, and in particular to a chip assembly with an inter-chip communication port capable of processing a layer of transport overhead (TOH) and a layer of path overhead (POH) of high order signals in transport telecommunication networks based on either SDH or SONET standards
The Synchronous Digital Hierarchy (SDH) and its North-American equivalent, the Synchronous Optical Network (SONET), are the globally accepted, closely related and compatible standards for data transmission in the public wide area network (WAN) domain. Recently, SDH/SONET has also been adopted by the ATM Forum as a recommended physical-layer transmission technology for ATM (Asynchronous Transfer Mode) network interfaces.
SONET and SDH govern interface parameters; rates, formats and multiplexing methods; operations, administration, maintenance and provisioning for high-speed signal transmission. SONET is primarily a set of North American standards with a fundamental transport rate beginning at approximately 52 Mb/s (i.e., 51.84 Mb/s), while SDH, principally used in Europe and Asia, defines a basic rate near 155 Mb/s (to be precise, 51.84xc3x973=155.52 Mb/s). From a transmission perspective, together they provide an international basis for supporting both existing and new services in the developed and developing countries.
For transmitting data, SDH and SONET use frame formats transmitted every 125 xcexcs (8000 frames/s). Because of compatibility between SDH and SONET, their basic frames are similarly structured, but differ in dimension which fact reflects the basic transmission rates of 155.52 and 51.84 Mb/s, respectively. To be more specific, a basic frame format of SDH is 9 rows of 270 bytes, or 2430 bits/frame, corresponding to an aggregate frame rate of 155.52 Mb/s. For SDH systems, the mentioned basic frame transmitted at the rate 155.52 Mb/s forms the fundamental building block called Synchronous Transport Module Level-1 (STM-1). For SONET systems, the basic frame has dimensions of 9 rows by 90 byte columns and, being transmitted at the rate 51.84 Mb/s, forms the appropriate fundamental building block called Synchronous Transport Signal Level-1 (STS-1 or OC-3). The transmission sequence in both SONET and SDH is as follows: the byte in the first row and the first column will be transmitted first; it is followed by the byte to its right, in the same row and so on, from left to right and from top to bottom.
Lower rate payloads (data portions transmitted at rates smaller than the basic ones) are mapped into the fundamental building blocks STM-1 and STS-1 respectively, while higher rate signals (payloads) are generated by byte-interleavingly multiplexing N fundamental building blocks to form STM-N signals (in SDH) or STS-N signals (in SONET). FIG. 1 explains the principle of byte-interleaved multiplexing on a specific example where four STM-1s are combined into one STM-4. The multiplexing is effected by byte-interleaved multiplexer (BIM) which produces a sequence of bytes where one byte from No. 1 building block is followed by one byte from No. 2 building block and so on. All low-speed signals must be frame-aligned prior to multiplexing.
STM-4/STM4c signal having a data rate 622.08 Mb/s (4xc3x97155.52 Mb/s) is one of the high order signals (payloads) in the SDH system. In SONET, it corresponds to STS-12/STS-12c having the same data rate. The signal STM4/STM-4c, being equivalent to STS-12/STS-12c, consists of four STM-1 or four STS-3 building blocks. The mentioned high order signal STM-4/STM4c can be transmitted in two ways.
A first way is to transmit it over at least four individual parallel paths: e.g., four STM-1 (or STS-3) paths. The signal transmitted along parallel paths is called STM-4. Each path may itself consist of up to three separate STS-1 paths, thus the STM-4 signal may comprise up to 12 individual paths, each transmitting an individual STM-l signal with its individual payload.
Alternatively, the signal can be transmitted as a concatenated stream over a single path; in that case the obtained signal (which is called STM-4c i.e., xe2x80x9cconcatenatedxe2x80x9d) is sent as a single combined payload in one synchronous payload envelope (SPE). The fact that the signal follows as a concatenated (multiframe) payload, as well as location of the SPE borders, are indicated using a number of so-called overhead bytes which are present in the frame.
Each basic frame of SONET or SDH comprises an information portion called Information Payload and a service portion called Overhead (OH), the latter being subdivided into a number of areas of overhead bytes (for example a Path Overhead layer POH, a Transport Overhead layer TOH), predestined for various service and control functions. One of such areas is a column of Path Overhead (POH) bytes, which is present both in the SDH and SONET frames and usually resides within the Information Payload area. POH supports performance monitoring, status feedback, signal labeling, user channel and a tracing function in a path, i.e. carries information about the signal from end to end through the entire transmission system. The POH is added and dismantled at or near service origination/termination points defining the path, and is not processed at intermediary nodes.
In SONET, the Transport overhead layer which is responsible for transport through the network, is broken into two partsxe2x80x94Line Overhead (LOH) and Section Overhead (SOH). Section overhead (SOH) is that overhead necessary for reliable communication between network elements such as terminals and regenerators. Line overhead (LOH) was established to allow reliable communication of necessary information between more complicated network elements such as terminals, digital cross-connects, multiplexers and switches.
In SDH, no Transport overhead is directly defined. However, any SDH basic frame comprises a Multiplex Section Overhead (MSOH) being analogous to LOH in SONET, and a Regenerator Section Overhead (RSOH) which play the part of SOH in SONET. FIG. 2 schematically illustrates an STM-1 frame with its overhead sections. It is therefore considered, that the layer of Transport overhead in SDH is actually formed by the mentioned MSOH and RSOH. POH column is considered a part of STM-1 payload. There is also a row of overhead bytes bearing information on so-called AU-pointers (administrative unit pointers) which are considered to belong neither to TOH nor to POH, and are analyzed separately.
It should be noted that, in a not concatenated signal, each of the component building blocks has its individual SPE and bears its own TOH and POH similarly to that shown in FIG. 2. In a concatenated signal having a single common SPE, the TOH area is assembled from individual TOHs of the component building blocks, while the POH column is one and common for the SPE, since it is intended for identifying and controlling a single path.
During decoding and checking of a SONET or SDH signal transmitted in a path, it is generally xe2x80x9cstripped downxe2x80x9d in layers by a control system, first decoding and checking the section information, then the line information and thereafter the path information. At each step, error checking is provided and errors (if detected) must be indicated either to the local control system, or to the originating path terminal element to inform about troubles in the path.
TranSwitch corporation entered the market with two products relevant to the subject of the present application. One of them is called SOT-3 (TXC-03003B) being an overhead terminator for STM-1/STS-3/STS-3c transmission applications. The other is PHAST-12 (TXC-06112) being a highly integrated SONET/SDH terminator device designed for ATM cell, frame, higher order multiplexing, and transmission applications. A single PHAST-12 device can terminate four individual STS-3c or STM-1 lines, as well or a single OC12/12c (corresponds to STM-4/4c) line. Each SONET/SDH terminator has an associated line interface block that performs clock recovery for four 155.52 Mbit/s signals or single 622.08 Mbit/s serial operation. A parallel line interface port and an expansion port together allow four PHAST devices to operate in unison for OC-48/STM-16 applications. Since the second device is designed for ATM applications, no capability to do re-timing on the receive side exists. To do the POH processing, four more chips would be required at the output side of the device.
IBM(copyright) Microelectronics Division, jointly with IBM Zurich Research, recently developed a so-called SMART chip designed in the frame of a Scalable and Modular Architecture for SDH/SONET Technology announced in the following websites: http://www.zurich.ibm.cor/projects/CS/smart.htm and http://www.zurich.ibm.com/Technology/SDH-SONET/SMART.htn. (The sites were last modified on 19.04.1999 and 26.04.1999, respectively.)
According to the announcement, the SMART chip is an integrated SDH/SONET framer technology, allowing multiple ATM (Asynchronous Transfer Mode) cell streams to be mapped into either four STS-1, four STM-1, one STS-3, one STM-4, or one STM-4c SDH/SONET frame(s), by using the same chip. Four identical SMART chips can operate in parallel to support one STM-16/STS-48 signal (to be distinguished from STM-16c/STS-48c) combining either sixteen 155-Mb/s or four 622-Mb/s ATM streams. SMART chip also includes clock recovery, clock synthesis functions and serializer/deserializer functions.
The basic component of SMART is a single 155 Mb/s macro performing the STM-1/STS-3c SDH/SONET frame processing. This component consists of a transmit part for creating SDH/SONET frames and mapping ATM cell or PPP packet streams into these frames and a receive part for receiving frames on the line interface side and extracting ATM cells or PPP packets from these frames. Beside the payload mapping this component creates/analyses all the section and path 25 overhead bytes defined in regional and international standards (ITU-T BellCore, ANSI, and ETSI) and scrambles the SDH/SONET frames. The macro contains already the necessary xe2x80x9chooksxe2x80x9d to interconnect several of these macros for distributed processing of STM-4/STS-12 and STM-4c/STS-12c frames.
Though functionality of the SMART chip has been announced, no specific information has been disclosed concerning its internal structure enabling the macros to be xe2x80x9chookedxe2x80x9d for distributed processing of the STM-4 and STM-4c signals.
It should be noted that, though four identical SMART chips are announced to operate in parallel to support one STM-16/STS-48 signal, and though it has been declared that SMART represents a building block approach covering the whole STM-x/STS-x family, no information is available on how concatenated versions of the above family can be treated. In other words, no technical solution has been described for supporting STM-xc/STS-xc signals.
It is therefore the object of the present invention to propose a solution to the above-mentioned problem of supporting concatenated high order SDH/SONET signals. A further object of the invention is to provide a technology for supporting any high order SDH/SONET signal, whether it is concatenated or not.
In the frame of the present application, the term xe2x80x9csupportingxe2x80x9d should be understood as handling an SDH/SONET signal (concatenated or non-concatenated high order signal, or a low order signal), with processing Transport Overhead bytes (TOH) and Path Overhead bytes (POH) thereof.
The above object can be achieved by a method of supporting a concatenated type of a high order SDH/SONET signal with processing TOH and POH thereof by:
utilizing a group of chips each being capable of supporting a lower order SDH/SONET signal with processing its TOH and POH, and
establishing inter-chip communication between said chips where one of them named a master chip is capable of coordinating operation of the remaining chips named slaves, thereby providing operation of said chips in accord as one unit.
The novelty of the method resides in the fact that it enables the concatenated high order signals (i.e., those having a multiframe synchronous payload envelope SPE) to be supported using a number of chips with a lower capability. Note that, for example, FIFO (First-In First-Out memory) of each of the component chips is adapted for handling the payload of a component said building block signal only.
In one particular version of the method, wherein said SDH/SONET high order signal is an N-fold lower order SDH/SONET signal named a building block signal; the method includes:
providing said group comprising N identical chips, wherein each of said chips having a FIFO,
arranging inter-chip communication between said chips in the group by enabling said master chip to coordinate said slaves so as to perform operations including the following:
synchronous handling, by each of the N chips including the master, 1/N-th portion of said concatenated high order signal with processing the TOH of a respective building block signal, and
processing the POH of said high order concatenated signal by said master chip,
thereby providing operation of said chips in accord as one unit having N-fold FIFO.
According to the most preferred version of the method, it also enables supporting a non-concatenated type of said SDH/SONET signal with processing Transport Overhead bytes (TOH) and Path Overhead bytes (POH) thereof, wherein said non-concatenated SDH/SONET high order signal is an N-fold lower order SDH/SONET signal named a building block signal having its TOH and POH;
the method comprises a step of arranging said inter-chip communication for enabling each of the chips to individually handle one respective said building block signal with processing the TOH and the POH thereof, thereby providing parallel handling of all said building block signals.
The method usually includes a preliminary step of defining the mode of operation of said module by a controller, for reversibly arranging the inter-chip communication between two modes, wherein one of the modes is a concatenated mode corresponding to said concatenated signal transmitted over a single path, and the other mode is a non-concatenated mode corresponding to the non-concatenated signal transmitted over at least N paths. In practice, it is accomplished by reconfiguring a so-called inter-chip port of a module comprising the group of chips.
Three pointer bytes H1 to H3 in the line overhead (LOH) of TOH indicate the location of the beginning of the SPE, which is very important for synchronizing the work of the chips in the module. Thus, the method includes determining the location of the beginning of the SPE. It should be noted, that the handling of the concatenated high order signal, upon determining the beginning of its synchronous payload envelope (SPE), includes detecting whether said SPE is multiframe by examining byte J1 of the POH and issuing a command by said master chip to inform said slaves on the beginning of their accord operation including synchronous handling the respective portions of said high order signal.
The accord operations include so-called FIFO operations, in other words, said synchronous handling the respective portions of the high order signal includes synchronous writing of its payload portions into the FIFOs of said chips respectively, and synchronous reading of said payload portions therefrom. The FIFO operations are required for buffering the incoming signals and synchronizing thereof with the clock of the receiving system (and vice versa)xe2x80x94so-called re-timing.
In the case of the non-concatenated signal, said payload portion is the information payload of one of the building block signals, i.e., a separate payload comprising its POH column.
In the case of the concatenated signal, said payload portion is a 1/N-th fragment of the multi-frame information payload of the high order SDH/SONET signal, wherein said chips handle respective portions of the multi-frame payload (and only the master chip handles POH of the whole concatenated signal).
Each of said respective portions of the multi-frame concatenated payload (i.e. portions of its synchronous payload envelope SPE, without TOH) comprises bytes belonging to a particular one of said N building blocks of the high order signal; these portions are defined according to so-called phases of the byte-interleaved multiplexing corresponding to the chips"" numbers in the module.
More particularly, the method includes strictly synchronizing the FIFOs operations of said chips by said master chip, i.e., simultaneous resetting read and write counters of all FIFOs in the module according to the master""s commands (such as transmit direction read/write address reset, receive direction read/write address reset) and simultaneously performing said FIFO operations by all the chips in the module.
Yet another operation, which becomes available owing to the inter-chip communication, is passing various alarms known in the SONET/SDH protocol (such as LOSxe2x80x94loss of signal, LOFxe2x80x94loss of frame, LOPxe2x80x94loss of pointer, AIS-Pxe2x80x94path alarm indication signal), if determined by at least one of the slave chips, to the master chip. The determined alarms are then reported from the complete module by generating common alarm signals.
The method further includes handling of parity calculations over the high order signal (or payload), using the inter-chip communication for producing information on errors, if determined. Each type of the parity calculations (say, calculation of overhead bytes B1, B2 or B3) is coordinated among the chips of the module in a serial fashion.
According to the basic version of the method, N is equal to 4, said SDf/SONET building block signal is the fundamental building block STM-1/STS-3, and said high order SDH/SONET signal is either STM-4/STS-12, or STM-4c/STS-12c. 
Consequently, each of said four identical chips is a chip capable of processing overhead of the first three layers of the SONET/SDH protocol for the SDH fundamental building block STM-1/STS-3 signal; said three layers being SOH, LOH and POH (in other words, TOH and POH).
For example, said chip may constitute a chip called TPOH (Transportxe2x80x94Path OverHead) developed by ECI Telecom(copyright) Ltd., Israel.
In the present application, a module comprising four such chips will be described to illustrate an example of the inter-chip port and its operation.
In another version of the method, the N is equal to 4, said SDH/SONET building block signal is a signal STM-4/STS-12, and said high order SDH/SONET signal is either STM-16/STS-48, or STM-16c/STS-48c. 
In this case, each of said four identical chips may constitute a SMART(copyright) chip developed by IBM(copyright) Inc. for processing TOH and POH of the SDH signal STM-4/STS-12.
According to a second aspect of the invention, for supporting a concatenated high order SDH/SONET signal in a module comprising a group of chips there is provided an inter-chip communication port; each of said chips is capable of supporting a lower order SDH/SONET signal while one of them named a master chip is capable of coordinating operation of the remaining chips named slaves.
According to one preferred embodiment, wherein said high order SDH/SONET signal has its Transport Overhead bytes (TOH) and Path Overhead bytes (POH), and is an N-fold lower order SDH/SONET signal named a building block signal and having its TOH and POH, said module comprises a group of N identical chips, each of said chips having a FIFO and being capable of processing TOH and POH of said building block signal;
said inter-chip communication port having a mode of operation for supporting a concatenated (i.e., having a multiframe payload) said high order signal, wherein said master chip is capable of controlling said slaves in a manner that:
each of said chips including the master is caused to handle a 1/N-th portion of said concatenated high order signal with processing the TOH of its respective building block signal, and
said master chip processes the POH of said high order concatenated signal,
thereby dividing said high order signal between the chips and causing them to work in accord (as one unit) to handle thereof.
According to the preferred embodiment of the inter-chip communication port, it is also capable of operating in another mode for handling a non-concatenated said high order SDHI/SONET signal, wherein each of the chips individually handles one said building block signal and processes the TOH and the POH thereof, thereby providing parallel handling of the building block signals.
In the most preferred embodiment, said inter-chip port is selectively operable in at least one of said operating modes including a concatenated mode corresponding to said concatenated signal, and a non-concatenated mode corresponding to said not concatenated signal; the inter-chip communication port thereby rendering said module capable of handling TOH and POH of the SDH/SONET high order signal being an N-fold SDH/SONET building block signal, both in the case where said signal is concatenated and in the case where it is not. In practice, the inter-chip communication port is re-configurable by a microcontroller.
In other words, in the concatenated mode all chips of the module operate in accord as one unit to handle a common multi-frame payload envelope (SPE) of said signal, and in the non-concatenated mode each of the chips operates individually to handle a synchronous payload envelope (SPE) of a corresponding said building block signal, the module thereby handling N said building block signals (i.e., N paths) in parallel.
For implementing the inter-chip communication, said module is capable of determining the location of the beginning of the SPE by examining pointer bytes H1 to H3 in the Transport overhead (TOH) and of detecting whether said SPE is multi-frame by examining byte J1 of the Path overhead (POH).
The inter-chip communication port is capable of issuing an alarm if the concatenation indicator does not match the preliminary selected mode of the module. This alarm is called xe2x80x9closs of pointer in the pathxe2x80x9d (LOP-P).
In the concatenated mode, said inter-chip port is capable of enabling said master chip to synchronize the FIFOs of said chips to provide simultaneous resetting the read and write counters thereof, and further to initiate synchronous FIFO read and write operations in all the chips in the module, thereby causing said FIFOs to handle respective payload portions of the concatenated high order signal. The master is adapted to indicate to slaves"" FIFOs when an overhead byte is handled, and when a payload byte is handled.
The inter-chip communication port comprises
a plurality of controllable serial channels between said chips, wherein in each of the serial channels a serial output port of one chip is connected to a serial input port of one adjacent chip, and
a plurality of controllable parallel channels between said chips, wherein in each of the parallel channels an output port of one (master) chip is connected to input ports of all other (slaves) chips;
said serial and parallel channels being operative both in the receiving and the transmitting directions.
The inter-chip communication port is controllable by a microcontroller.
One of the described serial channels is intended for collecting alarms indications, if determined by at least one of the slave chips, and passing thereof to the master chip. The mentioned alarm indications are, for example, those known in the SONET/SDH protocol (such as LOSxe2x80x94loss of signal, LOFxe2x80x94loss of frame, LOPxe2x80x94loss of pointer, AIS-Pxe2x80x94alarm indication signal in the path. The determined alarm indications are then to be reported from the master chip, as a resulting alarm indication of the complete module; the reporting is performed by means of generating alarm signals based on the collected complete information, via a separate serial channel. These operations are provided both in the concatenated, and in the non-concatenated modes.
The inter-chip communication port enables handling parity calculations in the module over the high order payload, for producing error information if errors are found, wherein said parity calculations (say, calculation of overhead bytes B1, B2 or B3) are coordinated among the four chips of the module in a serial fashion (i.e., using the serial channels for accumulating partial calculations performed at each of the chips). Calculations of B3 are performed in the concatenated mode only, while calculations of B1 and B2 are held in any mode. Parity calculations concerning overhead bytes B1, B2, and B3 are performed in different serial channels.
The parallel channels of the inter-chip communication port serve, for example, for indicating the beginning of SPE and for coordinating operations of the FIFOs, provided by the master chip to the slave chips in the concatenated mode.
According to the basic embodiment of the invention, N is equal to 4, said SDH/SONET building block signal is the SDH fundamental building block STM-1/STS-3, and said high order SDH/SONET signal is either STM-4/STS-12, or STM-4c/STS-12c. 
In this embodiment, each of said four identical chips is a chip capable of processing overhead of the first three layers of the SONET/SDH protocol for the SDH fundamental building block STM-1/STS-3 signal; said three layers being SOH, LOH and POH.
For example, a chip TPOH developed in ECI(copyright) Telecom Ltd, Israel, can be used for implementing the above-mentioned function. In this application, an assembly of four such chips will be described to illustrate an example of the inter-chip port and its operation.
In accordance with yet another embodiment of the invention, said N is equal to 4, said SDH/SONET building block is STM-4/STS-16, and said high order SDH/SONET signal is either STM-16/STS-48, or STM-16c/STS-48c. 
In the above-mentioned embodiment, said module may comprise four identical SMART(copyright) chips of IBM(copyright), each being capable of processing the TOH and POH for the building block signal STM-4/STM-4c. 
According to yet another aspect of the invention, there is provided a module for supporting a high order SDH signal STM-Nc (and optionally also STM-N) or a high order SONET signal STS-Nc (and optionally also STS-N), the module comprising four chips each being capable of handling an STM-(1/4)N or STS-(1/4)N building block signal, and an inter-chip communication port as described above. Other characteristic features of the inter-chip port and the module according to the invention will become apparent from the detailed description which follows.